Electronic Design

Reduce Power in Chip Designs with Sequential Clock Gating

Clock gating is one of the most frequently used techniques in RTL to reduce dynamic power consumption without affecting the functionality of the design. One method involves inserting gating conditions ...
EDN

Metastability and Clock Uncertainty in FPGA Designs

No discussion on FPGA design is complete without addressing the issues associated with transferring signals that are not synchronized to the clock into clocked logic. While this should be a digital ...
autoevolution

MTR Designs’ Ferrofluid Clock Will Bring a Touch of Awesome Into Your Office

If you’re into science and neat gadgets, maybe the Ferrofluid Clock from MTR Designs is the thing for you, as it manages to combine both into an elegant and unique timepiece that’s bound to become the ...
Semiconductor Engineering

Conquer Placement And Clock Tree Challenges In HPC Designs

High-performance computing (HPC) applications require IC designs with maximum performance. However, as process technology advances, achieving high performance has become increasingly challenging.
insider.si.edu

Designs for Table Clocks

Click to open image viewer. IIIF provides researchers rich metadata and media viewing options for comparison of works across cultural heritage collections. Visit the IIIF page to learn more. Five ...
THE WEEK

Did Apple rip off a famous Swiss clock's design?

As people fume over Apple's map update to iOS 6, the purveyor of iProducts finds itself in increasingly hot water, and now stands accused of copying the iconic (and trademarked) clocks of the Swiss ...
EDN

Designs with multiple clock domains: New tools avoid clock skew and reduce pattern counts

Nothing accelerates a testability engineer's receding hairline as the addition of further clock domains to the latest SoC or IC design. Avoiding clock skew during test is becoming one of the biggest ...
Semiconductor Engineering

Verification Of Multi-Clock Designs: The Bigger Picture

Yesterday’s SoCs are today’s blocks and sub-chips. The resultant combination of interfaces, protocols and performance objectives regularly results in many clock domains on a single chip. Often, this ...
Geeky Gadgets

Geeky Clocks – Design Your Own Clock

We have seen quite a few different geeky clocks here on Geeky Gadgets, and the latest one is a simple yet clever idea, the ‘Design Your Own Clock‘ clock. Basically, the Design Your Own Clock is a ...